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APCSAC
2006
IEEE
14 years 3 months ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
IEEECIT
2005
IEEE
14 years 3 months ago
Feedback Scheduling for Resource-Constrained Real-time Control Systems
Subject to limited computational resource, feedback scheduling aims to improve, or to optimize, the global control performance of real-time control systems. For the system that co...
Pingfang Zhou, Jianying Xie
FPL
2001
Springer
77views Hardware» more  FPL 2001»
14 years 2 months ago
Implementation of (Normalised) RLS Lattice on Virtex
We present an implementation of a complete RLS Lattice and Normalised RLS Lattice cores for Virtex. The cores accept 24-bit fixed point inputs and produce 24-bit fixed point predic...
Felix Albu, Jiri Kadlec, Christopher I. Softley, R...
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 6 months ago
Fetch Halting on Critical Load Misses
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael ...
IPPS
1998
IEEE
14 years 2 months ago
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...