We describe a simple scheme for mapping synchronous language models, in the form of Boolean Mealy Machines, into timed automata. The mapping captures certain idealized implementat...
This paper is about the modular compilation and distribution of a sub-class of Simulink programs [9] across networks using bounded FIFO queues. The problem is first addressed mat...
The paper first presents the integration options of what we call the Timing Description Language (TDL) with MathWorks' Simulink tools. Based on the paradigm of logical executi...
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
Abstract. Model-based development is supposed to improve the development efficiency by raising the abstraction level and generating applications instead of manually coding the appl...