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ASE
2010
129views more  ASE 2010»
13 years 7 months ago
Efficient monitoring of parametric context-free patterns
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...
Patrick O'Neil Meredith, Dongyun Jin, Feng Chen, G...
ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 4 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
DAC
1994
ACM
13 years 11 months ago
Probabilistic Analysis of Large Finite State Machines
Regarding nite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal veri cation problems. Recently, we ha...
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fab...
TCAD
2002
121views more  TCAD 2002»
13 years 7 months ago
Robust Boolean reasoning for equivalence checking and functional property verification
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, ...
JELIA
2000
Springer
13 years 11 months ago
A Logic for Modeling Decision Making with Dynamic Preferences
We present a framework for decision making with the possibility to express circumstance-dependent preferences among different alternatives for a decision. This new formalism, Order...
Marina De Vos, Dirk Vermeir