72 search results - page 12 / 15 » Abridged addressing: a low power memory addressing strategy |
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
JSA
2006
13 years 7 months ago
2006
Multimedia applications in general and video processing, such as the MPEG4 Visual stream decoders, in particular are increasingly popular and important workloads for future embedd...
SIGCOMM
2009
ACM
14 years 2 months ago
2009
ACM
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Transient errors are one of the major reasons for system downtime in many systems. While prior research has mainly focused on the impact of transient errors on datapath, caches an...
GLVLSI
2003
IEEE
14 years 23 days ago
2003
IEEE
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...