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» Abridged addressing: a low power memory addressing strategy
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ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 11 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
LCTRTS
2000
Springer
13 years 11 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra
ANCS
2005
ACM
14 years 1 months ago
SSA: a power and memory efficient scheme to multi-match packet classification
New network applications like intrusion detection systems and packet-level accounting require multi-match packet classification, where all matching filters need to be reported. Te...
Fang Yu, T. V. Lakshman, Martin Austin Motoyama, R...
CAL
2002
13 years 7 months ago
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Abstract-This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While ...
Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin...
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
14 years 1 months ago
A low complexity hardware architecture for motion estimation
This paper tackles the problem of accelerating The rest of this paper is organised as follows: section II motion estimation for video processing. A novel architecture details relat...
Daniel Larkin, Vlenti. Muresan, Noel E. O'Connor