36 search results - page 7 / 8 » Accelerating Architectural Simulation by Parallel Execution ... |
IPPS
2005
IEEE
14 years 28 days ago
2005
IEEE
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
JSA
2000
13 years 7 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
ICS
2001
Tsinghua U.
13 years 11 months ago
2001
Tsinghua U.
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
ICS
2009
Tsinghua U.
13 years 12 months ago
2009
Tsinghua U.
New static source routing algorithms for High Performance Computing (HPC) are presented in this work. The target parallel architectures are based on the commonly used fattree netw...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...