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HIPEAC
2009
Springer
14 years 15 days ago
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
DSD
2010
IEEE
172views Hardware» more  DSD 2010»
13 years 8 months ago
Adaptive Cache Memories for SMT Processors
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
Sonia López, Oscar Garnica, David H. Albone...
VTC
2006
IEEE
14 years 2 months ago
The WINNER B3G System MAC Concept
— The European IST research projects WINNER and WINNER II aim at developing a single new ubiquitous radio access system concept that can be adapted for use in a wide variety of m...
Mikael Sternad, Tommy Svensson, Göran Klang
TON
1998
107views more  TON 1998»
13 years 8 months ago
Migrating sockets--end system support for networking with quality of service guarantees
—We present an end system architecture designed to support networking with quality of service (QoS) guarantees. The protocol processing component of the architecture, called Migr...
David K. Y. Yau, Simon S. Lam
ITC
2003
IEEE
176views Hardware» more  ITC 2003»
14 years 1 months ago
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
Olivier Caty, Ismet Bayraktaroglu, Amitava Majumda...