This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
— The European IST research projects WINNER and WINNER II aim at developing a single new ubiquitous radio access system concept that can be adapted for use in a wide variety of m...
—We present an end system architecture designed to support networking with quality of service (QoS) guarantees. The protocol processing component of the architecture, called Migr...
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...