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DFT
2000
IEEE
106views VLSI» more  DFT 2000»
14 years 1 months ago
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
We present a configuration technique for a Large Area Integrated Circuit (LAIC) which is manufactured by wafer stepping. A LAIC consists of four identical subsystems, i.e., a subs...
Markus Rudack, Michael Redeker, Dieter Treytnar, O...
POPL
2012
ACM
12 years 5 months ago
A compiler and run-time system for network programming languages
Software-defined networks (SDNs) are a new implementation architecture in which a controller machine manages a distributed collection of switches, by instructing them to install ...
Christopher Monsanto, Nate Foster, Rob Harrison, D...
PC
2010
190views Management» more  PC 2010»
13 years 8 months ago
High-performance cone beam reconstruction using CUDA compatible GPUs
Compute unified device architecture (CUDA) is a software development platform that allows us to run C-like programs on the nVIDIA graphics processing unit (GPU). This paper prese...
Yusuke Okitsu, Fumihiko Ino, Kenichi Hagihara
CODES
2007
IEEE
14 years 4 months ago
Embedded software development on top of transaction-level models
Early embedded SW development with transaction-level models has been broadly promoted to improve SoC design productivity. But the proposed APIs only provide low-level read/write o...
Wolfgang Klingauf, Robert Günzel, Christian S...
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
14 years 1 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...