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IPPS
2006
IEEE
14 years 3 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
WETICE
2006
IEEE
14 years 3 months ago
Multi-Dimensional Performance Framework for Enterprise Knowledge Infrastructures
— Within service-oriented business environments, the non-routine processing of requests requires a greater degree of social interaction and learning in order to achieve an effect...
Joe Bolinger, Jay Ramanathan
WOWMOM
2006
ACM
94views Multimedia» more  WOWMOM 2006»
14 years 3 months ago
Performance Analysis and Enhancement of the Next Generation Cellular Networks
— As more and more wireless subscribers access the Internet through cellular networks, Internet data traffic, which is known to be long range dependent (LRD), will soon dominate...
Xiang Yu, Chunming Qiao, Xin Wang, Dahai Xu
CLUSTER
2005
IEEE
14 years 2 months ago
Implementation and Performance of Portals 3.3 on the Cray XT3
The Portals data movement interface was developed at Sandia National Laboratories in collaboration with the University of New Mexico over the last ten years. Portals is intended t...
Ron Brightwell, Trammell Hudson, Kevin T. Pedretti...
ICRA
2005
IEEE
99views Robotics» more  ICRA 2005»
14 years 2 months ago
Performance of Machines with Flexible Bodies Designed for Biomimetic Locomotion in Liquid Environments
— The self-propelled swimming performance of two prototypes designed to mimic the kinematics of real fish swimming at high Reynolds numbers is presented. The design methodology ...
Pablo Valdivia y Alvarado, Kamal Youcef-Toumi