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HPCA
2008
IEEE
14 years 9 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
14 years 2 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
GECCO
2004
Springer
14 years 2 months ago
Improving Generalisation Performance Through Multiobjective Parsimony Enforcement
This paper describes POPE-GP, a system that makes use of the NSGA-II multiobjective evolutionary algorithm as an alternative, parameter-free technique for eliminating program bloat...
Yaniv Bernstein, Xiaodong Li, Victor Ciesielski, A...
IEEEPACT
2002
IEEE
14 years 2 months ago
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
Gautham K. Dorai, Donald Yeung
ICC
2007
IEEE
14 years 3 months ago
Performance Analysis and Evaluation of VDSL2 Systems: Band-Plan Study
— In this paper we discuss the performance of different profiles of VDSL2 systems in a frequency range up to 12 MHz (bandplan 998 and 997, corresponding to the European region) u...
Hernán Córdova, Teun van der Veen, L...