Sciweavers

11384 search results - page 245 / 2277
» Achieved IPC Performance
Sort
View
CASES
2008
ACM
13 years 11 months ago
Exploring and predicting the architecture/optimising compiler co-design space
Embedded processor performance is dependent on both the underlying architecture and the compiler optimisations applied. However, designing both simultaneously is extremely difficu...
Christophe Dubach, Timothy M. Jones, Michael F. P....
DAC
2005
ACM
13 years 11 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
ERSA
2006
89views Hardware» more  ERSA 2006»
13 years 10 months ago
Multi-Mode Operator for SHA-2 Hash Functions
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arn...
SAB
2010
Springer
147views Optimization» more  SAB 2010»
13 years 7 months ago
Fractal Gene Regulatory Networks for Robust Locomotion Control of Modular Robots
Designing controllers for modular robots is difficult due to the distributed and dynamic nature of the robots. In this paper fractal gene regulatory networks are evolved to control...
Payam Zahadat, David Johan Christensen, Ulrik Pagh...
SAMOS
2010
Springer
13 years 7 months ago
Interleaving granularity on high bandwidth memory architecture for CMPs
—Memory bandwidth has always been a critical factor for the performance of many data intensive applications. The increasing processor performance, and the advert of single chip m...
Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex...