Sciweavers

11384 search results - page 269 / 2277
» Achieved IPC Performance
Sort
View
DFT
2005
IEEE
126views VLSI» more  DFT 2005»
14 years 3 months ago
Analysis and Testing for Error Tolerant Motion Estimation
We propose a novel system-level error tolerance approach specifically targeted for multimedia compression algorithms. In particular we focus on the motion estimation process perf...
Hyukjune Chung, Antonio Ortega
PATMOS
2005
Springer
14 years 3 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
MCS
2004
Springer
14 years 3 months ago
Dynamic Classifier Selection by Adaptive k-Nearest-Neighbourhood Rule
Despite the good results provided by Dynamic Classifier Selection (DCS) mechanisms based on local accuracy in a large number of applications, the performances are still capable of ...
Luca Didaci, Giorgio Giacinto
DSD
2004
IEEE
132views Hardware» more  DSD 2004»
14 years 1 months ago
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
CASES
2005
ACM
13 years 11 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt