Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
Efficient resource usage is a key to achieving better performance in cluster systems. Previously, most research in this area has focused on balancing the load of each node to use...
Min Choi, Jung-Lok Yu, Hojoong Kim, Seung Ryoul Ma...
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo K...
In this paper we present LX-Parser, a probabilistic, robust constituency parser for Portuguese. This parser achieves ca. 88% f-score in the labeled bracketing task, thus reaching ...
In this paper an improved version of the graded precision localization algorithm GRADELOC, called IGRADELOC is proposed. The performance of GRADELOC is dependent on the regions fo...