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DSN
2007
IEEE
14 years 3 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
CLUSTER
2003
IEEE
14 years 2 months ago
Improving Performance of a Dynamic Load Balancing System by Using Number of Effective Tasks
Efficient resource usage is a key to achieving better performance in cluster systems. Previously, most research in this area has focused on balancing the load of each node to use...
Min Choi, Jung-Lok Yu, Hojoong Kim, Seung Ryoul Ma...
CASES
2007
ACM
14 years 23 days ago
Performance evaluation and optimization of dual-port SDRAM architecture for mobile embedded systems
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo K...
LREC
2010
117views Education» more  LREC 2010»
13 years 10 months ago
Top-Performing Robust Constituency Parsing of Portuguese: Freely Available in as Many Ways as you Can Get it
In this paper we present LX-Parser, a probabilistic, robust constituency parser for Portuguese. This parser achieves ca. 88% f-score in the labeled bracketing task, thus reaching ...
João Silva, António Branco, Patricia...
CORR
2010
Springer
167views Education» more  CORR 2010»
13 years 8 months ago
Performance Analysis of an Improved Graded Precision Localization Algorithm for Wireless Sensor Networks
In this paper an improved version of the graded precision localization algorithm GRADELOC, called IGRADELOC is proposed. The performance of GRADELOC is dependent on the regions fo...
Sanat Sarangi, Subrat Kar