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RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
IPPS
1997
IEEE
13 years 12 months ago
A Reliable Hardware Barrier Synchronization Scheme
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...
CCS
2008
ACM
13 years 9 months ago
A security architecture for transient trust
In extraordinary situations, certain individuals may require access to information for which they are not normally authorized. For example, to facilitate rescue of people trapped ...
Cynthia E. Irvine, Timothy E. Levin, Paul C. Clark...
ICPP
2006
IEEE
14 years 1 months ago
Data Transfers between Processes in an SMP System: Performance Study and Application to MPI
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
Darius Buntinas, Guillaume Mercier, William Gropp
HPCA
2008
IEEE
14 years 8 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...