73 search results - page 12 / 15 » Activity-Driven Synthesis of State Machines |
FDL
2003
IEEE
14 years 2 months ago
2003
IEEE
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
NEUROSCIENCE
2001
Springer
14 years 2 months ago
2001
Springer
We propose a theoretical framework for specification and analysis of a class of learning problems that arise in open-ended environments that contain multiple, distributed, dynamic...
DAC
2000
ACM
14 years 10 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
In this paper we propose an on-chip bus PMU which makes accurate estimates of system power consumption from a first-order linear power model by utilizing system-level activity in...