433 search results - page 55 / 87 » Activity-driven clock design for low power circuits |
153
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SLIP
2009
ACM
16 years 13 days ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
154
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DATE
2009
IEEE
16 years 21 days ago
2009
IEEE
There is a growing concern about timing errors resulting from design marginalities and the effects of circuit aging on speed-paths in logic circuits. This paper presents a low ove...
146
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FPGA
2004
ACM
15 years 11 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
169
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DAC
2011
ACM
14 years 5 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
150
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GLVLSI
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents a hybrid adiabatic content addressable memory (CAM). The CAM uses an adiabatic switching technique to reduce the energy consumption in the match line while kee...