140 search results - page 21 / 28 » Activity-sensitive architectural power analysis for the cont... |
GLOBECOM
2009
IEEE
13 years 5 months ago
2009
IEEE
Abstract--In this paper we investigate hardware implementations of ciphering algorithms, SNOW 3G and the Advanced Encryption Standard (AES), for the acceleration of the protocol st...
JUCS
2000
13 years 7 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
COOPIS
2002
IEEE
14 years 13 days ago
2002
IEEE
Rapid advances in networking, hardware, and middleware technologies are facilitating the development and deployment of complex grid applications, such as large-scale distributed co...
HICSS
2003
IEEE
14 years 23 days ago
2003
IEEE
The aim of this study is to identify factors that improve the performance of integrated supply chains (SCs). We developed the ‘extended strategic alignment model’ based on the ...