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» Adaptive Cache Memories for SMT Processors
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ISCA
2009
IEEE
276views Hardware» more  ISCA 2009»
14 years 2 months ago
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (...
Yuejian Xie, Gabriel H. Loh
NA
2010
87views more  NA 2010»
13 years 6 months ago
A note on the O(n)-storage implementation of the GKO algorithm and its adaptation to Trummer-like matrices
We propose a new O(n)-space implementation of the GKO-Cauchy algorithm for the solution of linear systems where the coefficient matrix is Cauchy-like. Moreover, this new algorithm...
Federico Poloni
MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
14 years 1 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
ICS
2005
Tsinghua U.
14 years 1 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal
TVLSI
2008
150views more  TVLSI 2008»
13 years 7 months ago
Data Memory Subsystem Resilient to Process Variations
As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance o...
M. Bennaser, Yao Guo, Csaba Andras Moritz