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ICASSP
2008
IEEE
14 years 2 months ago
A normalized adaptation scheme for the convex combination of two adaptive filters
Adaptive filtering schemes are subject to different tradeoffs regarding their steady-state misadjustment, speed of convergence and tracking performance. To alleviate these comp...
Luis Antonio Azpicueta-Ruiz, Aníbal R. Figu...
ISQED
2005
IEEE
162views Hardware» more  ISQED 2005»
14 years 1 months ago
Controlled-Load Limited Switch Dynamic Logic Circuit
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
JVCIR
2006
140views more  JVCIR 2006»
13 years 8 months ago
Improved H.264 rate control by enhanced MAD-based frame complexity prediction
This paper presents a revised rate control scheme based on an improved frame complexity measure. Rate control adopted by both MPEG-4 VM18 and H.264/AVC use a quadratic rate-distor...
Xiaoquan Yi, Nam Ling
NOCS
2008
IEEE
14 years 2 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
TVLSI
2008
164views more  TVLSI 2008»
13 years 8 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...