Controlled-Load Limited Switch Dynamic Logic Circuit

Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounces. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

• Type: Conference
• Year: 2005
• Where: ISQED
• Authors: Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Nowka, Robert K. Montoye, Richard B. Brown
• Keywords: 64-bit Rotator Circuit, Hardware, ISQED 2005, Performance Logic Circuit, Switch Dynamic Logic