349 search results - page 50 / 70 » Adaptive Software Transactional Memory |
ISCA
2012
IEEE
12 years 8 days ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
POPL
2006
ACM
14 years 10 months ago
2006
ACM
The movement to multi-core processors increases the need for simpler, more robust parallel programming models. Atomic sections have been widely recognized for their ease of use. T...
ISPASS
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes the use of microprocessor performance counters for online measurement of complete system power consumption. While past studies have demonstrated the use of per...
C3S2E
2009
ACM
14 years 1 months ago
2009
ACM
Most database systems (DBMSs) today are operating on servers equipped with magnetic disks. In our contribution, we want to motivate the use of two emerging and striking technologi...
DATE
2009
IEEE
14 years 4 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...