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MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 7 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
EAAI
2008
128views more  EAAI 2008»
13 years 9 months ago
Dual heuristic programming based nonlinear optimal control for a synchronous generator
This paper presents the design of an infinite horizon nonlinear optimal neurocontroller that replaces the conventional automatic voltage regulator and the turbine governor (CONVC)...
Jung-Wook Park, Ronald G. Harley, Ganesh K. Venaya...
DATE
2007
IEEE
133views Hardware» more  DATE 2007»
14 years 3 months ago
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Be...
Hazem Moussa, Olivier Muller, Amer Baghdadi, Miche...
ECBS
2004
IEEE
93views Hardware» more  ECBS 2004»
14 years 28 days ago
Domain Independent Generative Modeling
Model Integrated Computing employs domainspecific modeling languages for the design of Computer Based Systems and automatically generates their implementation. These system models...
Branislav Kusy, Ákos Lédeczi, Miklos...
ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
13 years 11 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...