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» Adaptive Website Design Using Caching Algorithms
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DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 18 days ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
HIPEAC
2009
Springer
13 years 11 months ago
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
ICCD
2004
IEEE
126views Hardware» more  ICCD 2004»
14 years 4 months ago
Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling
Simultaneous Multithreading (SMT) is emerging as an effective microarchitecture model to increase the utilization of resources in modern super-scalar processors. However, co-sched...
Joshua L. Kihm, Daniel A. Connors
ICDE
2008
IEEE
148views Database» more  ICDE 2008»
14 years 2 months ago
Automated physical design in database caches
Abstract— Performance of proxy caches for database federations that serve a large number of users is crucially dependent on its physical design. Current techniques, automated or ...
Tanu Malik, Xiaodan Wang, Randal C. Burns, Debabra...
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 1 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...