Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application...
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
We propose a low-delay low-complexity end-to-end video transmission system that integrates the latest scalable H.264 codec and the full-rate full-diversity quasi-orthogonal space-...
Mohammad K. Jubran, Manu Bansal, Lisimachos P. Kon...
In this paper, we present a hierarchical evolutionary approach to hardware/software partitioning for real-time embedded systems. In contrast to most of previous approaches, we app...