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» Address Register Assignment for Reducing Code Size
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TCAD
2008
201views more  TCAD 2008»
13 years 6 months ago
Bitmask-Based Code Compression for Embedded Systems
Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge ...
Seok-Won Seong, Prabhat Mishra
ACMMSP
2004
ACM
92views Hardware» more  ACMMSP 2004»
14 years 4 days ago
Instruction combining for coalescing memory accesses using global code motion
Instruction combining is an optimization to replace a sequence of instructions with a more efficient instruction yielding the same result in a fewer machine cycles. When we use it...
Motohiro Kawahito, Hideaki Komatsu, Toshio Nakatan...
VISUALIZATION
1999
IEEE
13 years 11 months ago
A Multi-Threaded Streaming Pipeline Architecture for Large Structured Data Sets
Computer simulation and digital measuring systems are now generating data of unprecedented size. The size of data is becoming so large that conventional visualization tools are in...
C. Charles Law, Ken Martin, William J. Schroeder, ...
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
14 years 3 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 7 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...