114 search results - page 17 / 23 » Address Register Assignment for Reducing Code Size |
TC
1998
13 years 6 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
ASAP
2010
IEEE
13 years 8 months ago
2010
IEEE
Recent research has proposed security-critical real-time embedded systems with provably-strong information containment through the use of hardware-enforced execution leases. Execut...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
FAST
2008
13 years 9 months ago
2008
Ever-increasing complexity of large-scale applications and continuous increases in sizes of the data they process make the problem of maximizing performance of such applications a...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...