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INFOCOM
2008
IEEE
14 years 1 months ago
Beyond TCAMs: An SRAM-Based Parallel Multi-Pipeline Architecture for Terabit IP Lookup
—Continuous growth in network link rates poses a strong demand on high speed IP lookup engines. While Ternary Content Addressable Memory (TCAM) based solutions serve most of toda...
Weirong Jiang, Qingbo Wang, Viktor K. Prasanna
FCCM
2000
IEEE
144views VLSI» more  FCCM 2000»
13 years 12 months ago
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines
Mapping computations written in high-level programming languages to FPGA-based computing engines requires programmers to generate the datapath responsible for the core of the comp...
Pedro C. Diniz, Joonseok Park
ACSAC
2004
IEEE
13 years 11 months ago
A Dynamic Technique for Eliminating Buffer Overflow Vulnerabilities (and Other Memory Errors)
Buffer overflow vulnerabilities are caused by programming errors that allow an attacker to cause the program to write beyond the bounds of an allocated memory block to corrupt oth...
Martin C. Rinard, Cristian Cadar, Daniel Dumitran,...
VLSISP
1998
128views more  VLSISP 1998»
13 years 7 months ago
A Low Power DSP Engine for Wireless Communications
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
Ingrid Verbauwhede, Mihran Touriguian
MEMOCODE
2010
IEEE
13 years 5 months ago
Feldspar: A domain specific language for digital signal processing algorithms
A new language, Feldspar, is presented, enabling high-level and platform-independent description of digital signal processing (DSP) algorithms. Feldspar is a pure functional langua...
Emil Axelsson, Koen Claessen, Gergely Dévai...