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» Address generation for memories containing multiple arrays
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AINA
2005
IEEE
14 years 1 months ago
Fast and Scalable Multi-TCAM Classification Engine for Wide Policy Table Lookup
With the explosive growth of Internet traffic, the next generation switches are designed to provide forwarding speed up to 10Gbps or above. To meet the challenges of delivering wi...
Nen-Fu Huang, Kwei-Bor Chen, Whai-En Chen
CODES
2004
IEEE
13 years 11 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
14 years 23 days ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
GECCO
2008
Springer
155views Optimization» more  GECCO 2008»
13 years 8 months ago
Towards memoryless model building
Probabilistic model building methods can render difficult problems feasible by identifying and exploiting dependencies. They build a probabilistic model from the statistical prope...
David Iclanzan, Dumitru Dumitrescu
TJS
2002
135views more  TJS 2002»
13 years 7 months ago
HPCVIEW: A Tool for Top-down Analysis of Node Performance
Although it is increasingly difficult for large scientific programs to attain a significant fraction of peak performance on systems based on microprocessors with substantial instr...
John M. Mellor-Crummey, Robert J. Fowler, Gabriel ...