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RTSS
2006
IEEE
14 years 1 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
TPDS
2010
159views more  TPDS 2010»
13 years 6 months ago
Exploring In-Situ Sensing Irregularity in Wireless Sensor Networks
The circular sensing model has been widely used to estimate performance of sensing applications in existing analysis and simulations. While this model provides valuable high-level...
Joengmin Hwang, Tian He, Yongdae Kim
DAC
2002
ACM
14 years 8 months ago
Software synthesis from synchronous specifications using logic simulation techniques
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
Yunjian Jiang, Robert K. Brayton
ISCA
2009
IEEE
192views Hardware» more  ISCA 2009»
14 years 2 months ago
A case for bufferless routing in on-chip networks
Buffers in on-chip networks consume significant energy, occupy chip area, and increase design complexity. In this paper, we make a case for a new approach to designing on-chip in...
Thomas Moscibroda, Onur Mutlu
AIED
2005
Springer
14 years 1 months ago
THESPIAN: An Architecture for Interactive Pedagogical Drama
Interactive drama is increasingly being used as a pedagogical tool in a wide variety of computer-based learning environments. However, the effort required to build interactive dram...
Mei Si, Stacy C. Marsella, David V. Pynadath