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GECCO
2007
Springer
179views Optimization» more  GECCO 2007»
14 years 1 months ago
A destructive evolutionary process: a pilot implementation
This paper describes the application of evolutionary search to the problem of Flash memory wear-out. The operating parameters of Flash memory are notoriously difficult to determin...
Joe Sullivan, Conor Ryan
LCTRTS
2007
Springer
14 years 1 months ago
External memory page remapping for embedded multimedia systems
As memory speeds and bus capacitances continue to rise, external memory bus power will make up an increasing portion of the total system power budget for system-on-a-chip embedded...
Ke Ning, David R. Kaeli
IEEEPACT
2006
IEEE
14 years 1 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
ASPLOS
1989
ACM
13 years 11 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 11 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah