241 search results - page 38 / 49 » Advanced Loop Optimizations for Parallel Computers |
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
In recent years, several approaches have been proposed to use profile information in compiler optimization. This profile information can be used at the source level to guide loo...
CGO
2010
IEEE
14 years 3 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
FCCM
2011
IEEE
13 years 5 days ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
IPPS
2008
IEEE
14 years 2 months ago
2008
IEEE
In the near future, wireless sensor networks (WSN) performing sensing and communication tasks will be widely deployed as technology rapidly advances. Communication is one of the e...
CCGRID
2001
IEEE
14 years 2 days ago
2001
IEEE
To ameliorate the need to spend significant programmer time modifying parallel programs to achieve highperformance, while maintaining compact, comprehensible source codes, this pa...