66 search results - page 10 / 14 » Aggregating processor free time for energy reduction |
ISCA
2010
IEEE
14 years 17 days ago
2010
IEEE
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions...
ICIP
2002
IEEE
14 years 9 months ago
2002
IEEE
A new color quantization (CQ) technique and its VLSI implementation is introduced. It is based on image split into windows and uses Kohonen Self Organized Neural Network Classifie...