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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 5 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
DSN
2002
IEEE
14 years 2 months ago
Performance Analysis of a Consensus Algorithm Combining Stochastic Activity Networks and Measurements
Protocols which solve agreement problems are essential building blocks for fault tolerant distributed applications. While many protocols have been published, little has been done ...
Andrea Coccoli, Péter Urbán, Andrea ...
GECCO
2010
Springer
158views Optimization» more  GECCO 2010»
14 years 1 months ago
A genetic algorithm to improve linux kernel performance on resource-constrained devices
As computers become increasingly mobile, users demand more functionality, longer battery-life, and better performance from mobile devices. In response, chipset fabricators are foc...
James Kukunas, Robert D. Cupper, Gregory M. Kapfha...
PPSN
1994
Springer
14 years 1 months ago
A Representation Scheme To Perform Program Induction in a Canonical Genetic Algorithm
This paper studies Genetic Programming (GP) and its relation to the Genetic Algorithm (GA). GP uses a GA approach to breed successive populations of programs, represented in the ch...
Mark Wineberg, Franz Oppacher
SIGARCH
2008
94views more  SIGARCH 2008»
13 years 9 months ago
Parallelization, performance analysis, and algorithm consideration of Hough transform on chip multiprocessors
This paper presents a parallelization framework for emerging applications on the future chip multiprocessors (CMPs). With the continuing prevalence of CMP and the number of on-die...
Wenlong Li, Yen-Kuang Chen