A cache-defect-aware code placement algorithm for improving the performance of processors

— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that faultfree sections can function independently. Many fault tolerant techniques for improving the yield of processors with a cache memory have been proposed [3][4][5]. In this paper, we propose a defect-aware code placement technique which offsets the performance degradation of a processor with a defective cache memory. To the best of our knowledge, this is the first compiler-based technique which offsets the performance degradation due to cache defects. Experiments demonstrate that the technique can compensate the performance degradation even when 5% of cache lines are faulty. In some cases the technique was able to offset the impact even in presence of 25% faulty cache-lines.

• Type: Conference
• Year: 2005
• Where: ICCAD
• Authors: Tohru Ishihara, Farzan Fallah
• Keywords: Code Placement Technique, Defective Cache Memory, Hardware, ICCAD 2005, Performance Degradation