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ICCAD
2009
IEEE
159views Hardware» more  ICCAD 2009»
13 years 5 months ago
First steps towards SAT-based formal analog verification
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
Saurabh K. Tiwary, Anubhav Gupta, Joel R. Phillips...
FPGA
2005
ACM
122views FPGA» more  FPGA 2005»
14 years 1 months ago
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
Yan Lin, Fei Li, Lei He
IJHPCA
2008
75views more  IJHPCA 2008»
13 years 7 months ago
Towards Ultra-High Resolution Models of Climate and Weather
We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
Michael F. Wehner, Leonid Oliker, John Shalf
VL
2003
IEEE
128views Visual Languages» more  VL 2003»
14 years 27 days ago
Development and evaluation of a model of programming errors
Models of programming and debugging suggest many causes of errors, and many classifications of error types exist. Yet, there has been no attempt to link causes of errors to these ...
Andrew Jensen Ko, Brad A. Myers
RECOMB
2003
Springer
14 years 8 months ago
Joint classifier and feature optimization for cancer diagnosis using gene expression data
Recent research has demonstrated quite convincingly that accurate cancer diagnosis can be achieved by constructing classifiers that are designed to compare the gene expression pro...
Balaji Krishnapuram, Lawrence Carin, Alexander J. ...