78 search results - page 6 / 16 » Algorithms for Quad-Double Precision Floating Point Arithmet... |
ASAP
2004
IEEE
13 years 11 months ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...
ARITH
2005
IEEE
14 years 1 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
FCCM
1997
IEEE
13 years 11 months ago
1997
IEEE
Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simpl...
ARITH
1999
IEEE
13 years 12 months ago
1999
IEEE
A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm i...
TVLSI
2008
13 years 7 months ago
2008
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...