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» Aligators for Arrays (Tool Paper)
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DAC
1996
ACM
13 years 11 months ago
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
FPL
2008
Springer
110views Hardware» more  FPL 2008»
13 years 9 months ago
Automatic generation of run-time parameterizable configurations
In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can ...
Karel Bruneel, Dirk Stroobandt
CORR
2007
Springer
105views Education» more  CORR 2007»
13 years 7 months ago
Empirical Evaluation of Four Tensor Decomposition Algorithms
Higher-order tensor decompositions are analogous to the familiar Singular Value Decomposition (SVD), but they transcend the limitations of matrices (second-order tensors). SVD is ...
Peter D. Turney
TVLSI
2008
133views more  TVLSI 2008»
13 years 7 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
FPL
2010
Springer
170views Hardware» more  FPL 2010»
13 years 5 months ago
IP Based Configurable SIMD Massively Parallel SoC
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
Mouna Baklouti, Mohamed Abid, Philippe Marquet, Je...