This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John ...
In this paper we present a methodology and set of tools which assist the construction of applications from components, by separating the issues of transmission policy from compone...
Scott M. Walker, Alan Dearle, Graham N. C. Kirby, ...
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
Abid Rafique, Nachiket Kapre, George A. Constantin...
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
Abstract. We propose an asynchronous protocol for general multiparty computation with perfect security and communication complexity O(n2 |C|k) where n is the number of parties, |C|...