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» Alternative Test Methods Using IEEE 1149.4
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DSD
2002
IEEE
86views Hardware» more  DSD 2002»
14 years 2 months ago
Using Formal Tools to Study Complex Circuits Behaviour
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
Paul Amblard, Fabienne Lagnier, Michel Lévy
ICCAD
2007
IEEE
135views Hardware» more  ICCAD 2007»
14 years 6 months ago
A selective pattern-compression scheme for power and test-data reduction
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
Chia-Yi Lin, Hung-Ming Chen
ATS
2003
IEEE
98views Hardware» more  ATS 2003»
14 years 2 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
ICCAD
1999
IEEE
115views Hardware» more  ICCAD 1999»
14 years 1 months ago
An approach for improving the levels of compaction achieved by vector omission
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...
Irith Pomeranz, Sudhakar M. Reddy
BMCBI
2008
121views more  BMCBI 2008»
13 years 9 months ago
A simple and fast heuristic for protein structure comparison
Background: Protein structure comparison is a key problem in bioinformatics. There exist several methods for doing protein comparison, being the solution of the Maximum Contact Ma...
David A. Pelta, Juan Ramón González,...