3 search results - page 1 / 1 » An 830mW, 586kbps 1024-bit RSA chip design |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents an RSA hardware design that simultaneously achieves high-performance and lowpower. A bit-oriented, split modular multiplication algorithm and architecture are ...
EUROCRYPT
2007
Springer
14 years 2 months ago
2007
Springer
Significant progress in the design of special purpose hardware for supporting the Number Field Sieve (NFS) has been made. From a practical cryptanalytic point of view, however, no...
CHES
2005
Springer
2005
Springer
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
14 years 1 months ago
Motivated by the goal of factoring large integers using the Number Field Sieve, several special-purpose hardware designs have been recently proposed for solving large sparse system...