23 search results - page 4 / 5 » An ASIC perspective on FPGA optimizations |
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
CHES
2011
Springer
12 years 7 months ago
2011
Springer
A lightweight and secure key storage scheme using silicon Physical Unclonable Functions (PUFs) is described. To derive stable PUF bits from chip manufacturing variations, a lightwe...
FPGA
2005
ACM
14 years 27 days ago
2005
ACM
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
ISLPED
2005
ACM
14 years 28 days ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
FPL
2005
Springer
14 years 27 days ago
2005
Springer
With the onset of Gigabit networks, current generation networking components will soon be insufficient for numerous reasons: most notably because existing methods cannot support h...