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CODES
2007
IEEE
14 years 3 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
ISCA
2007
IEEE
167views Hardware» more  ISCA 2007»
14 years 3 months ago
New cache designs for thwarting software cache-based side channel attacks
Software cache-based side channel attacks are a serious new class of threats for computers. Unlike physical side channel attacks that mostly target embedded cryptographic devices,...
Zhenghong Wang, Ruby B. Lee
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 3 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
GECCO
2007
Springer
241views Optimization» more  GECCO 2007»
14 years 2 months ago
Binary ant algorithm
When facing dynamic optimization problems the goal is no longer to find the extrema, but to track their progression through the space as closely as possible. Over these kind of ov...
Carlos Fernandes, Agostinho C. Rosa, Vitorino Ramo...
INFOCOM
2006
IEEE
14 years 2 months ago
Policy-Based Resource Management and Service Provisioning in GMPLS Networks
— Emerging network applications tend to be built over heterogeneous network resources spanning multiple management domains. Many such applications have dynamic demands for dedica...
Xi Yang, Tom Lehman, Chris Tracy, Jerry Sobieski, ...