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» An Access Timing Measurement Unit of Embedded Memory
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125
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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 9 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
144
Voted
RTCSA
2007
IEEE
15 years 10 months ago
A NOR Emulation Strategy over NAND Flash Memory
This work is motivated by a strong market demand in the replacement of NOR flash memory with NAND flash memory to cut down the cost in many embedded-system designs, such as mobi...
Jian-Hong Lin, Yuan-Hao Chang, Jen-Wei Hsieh, Tei-...
122
Voted
LCTRTS
2010
Springer
15 years 10 months ago
Operation and data mapping for CGRAs with multi-bank memory
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunh...
133
Voted
VTS
2007
IEEE
103views Hardware» more  VTS 2007»
15 years 10 months ago
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester
In SoC designs, limited test access to internal cores, lowcost external tester’s lack of accuracy and slow frequencies make application of at-speed tests impractical. Therefore,...
Matthieu Tuna, Mounir Benabdenbi, Alain Greiner
106
Voted
EMSOFT
2009
Springer
15 years 10 months ago
Probabilistic modeling of data cache behavior
In this paper, we propose a formal analysis approach to estimate the expected (average) data cache access time of an application across all possible program inputs. Towards this g...
Vinayak Puranik, Tulika Mitra, Y. N. Srikant