120 search results - page 6 / 24 » An Accurate Interconnection Length Estimation for Computer L... |
VLSID
1999
IEEE
14 years 25 days ago
1999
IEEE
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
EURODAC
1994
IEEE
14 years 21 days ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
INFOCOM
2010
IEEE
13 years 7 months ago
2010
IEEE
—Previous packet length optimizations for sensor networks often employ a fixed optimal length scheme, while in this study we present DPLC, a Dynamic Packet Length Control scheme...
DAC
1999
ACM
14 years 9 months ago
1999
ACM
Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
ICES
2003
Springer
14 years 1 months ago
2003
Springer
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...