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» An Analysis of Delay Based PUF Implementations on FPGA
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ICANN
2005
Springer
14 years 1 months ago
A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
Martin J. Pearson, Ian Gilhespy, Kevin N. Gurney, ...
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 3 days ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ICMCS
2006
IEEE
142views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Complexity Analysis of H.264 Decoder for FPGA Design
— A major challenge in the design of any real time system is the proper selection of implementation and platform alternatives. In this paper, a suitable FPGA-based design of the ...
Tuomas Lindroth, Nastooh Avessta, Jukka Teuhola, T...
FPGA
2010
ACM
227views FPGA» more  FPGA 2010»
14 years 4 months ago
On-line sensing for healthier FPGA systems
Electronic systems increasingly suffer from component variation, thermal hotspots, uneven wearout, and other subtle physical phenomena. Systems based on FPGAs have unique opportun...
Kenneth M. Zick, John P. Hayes
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...