51 search results - page 9 / 11 » An Analytical Model of Multistage Interconnection Networks |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
ISCAPDCS
2003
13 years 9 months ago
2003
The development and use of cluster based computing is increasingly becoming an effective approach for solving high performance computing problems. The trend of moving away from sp...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
Getting agents in the Internet, and in networks in general, to invest in and deploy security features and protocols is a challenge, in particular because of economic reasons arisi...
EUROPAR
1997
Springer
13 years 11 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
ISCAS
2003
IEEE
14 years 24 days ago
2003
IEEE
Abstract— The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of...