We present an approach for describing tests using nondeterministic test generation programs. To write such programs, we introduce UDITA, a Java-based language with non-determinist...
Milos Gligoric, Tihomir Gvero, Vilas Jagannath, Sa...
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
SystemC is a popular modeling language which can be used to specify systems at bstraction level. Currently, SystemC tools can not cope with SystemC models for which the module hie...
The goal of input-output modeling is to apply a test input to a system, analyze the results, and learn something useful from the causeeffect pair. Any automated modeling tool that...
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...