89 search results - page 6 / 18 » An Architecture for Combined Test Data Compression and Abort... |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The growing computational and storage needs of several scientific applications mandate the deployment of extreme-scale parallel machines, such as IBM’s Blue Gene/L which can acc...
DCC
2007
IEEE
14 years 7 months ago
2007
IEEE
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
SPE
2008
13 years 7 months ago
2008
The innate verbosity of the Extensible Markup Language remains one of its main weaknesses, especially when large XML documents are concerned. This problem can be solved with the a...
TVLSI
2002
13 years 7 months ago
2002
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This paper shows that by creating functional scan chains at the register-transfer level (RTL), not only the timing of the circuit can be improved, but also the test data compressi...