Sciweavers

1322 search results - page 104 / 265
» An Architecture for Distributed Simulation Games
Sort
View
135
Voted
ISCA
2005
IEEE
126views Hardware» more  ISCA 2005»
15 years 9 months ago
A Tree Based Router Search Engine Architecture with Single Port Memories
Pipelined forwarding engines are used in core routers to meet speed demands. Tree-based searches are pipelined across a number of stages to achieve high throughput, but this resul...
Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Su...
118
Voted
HPCC
2009
Springer
15 years 8 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
124
Voted
ICPADS
1994
IEEE
15 years 7 months ago
Efficient Fault Tolerance: An Approach to Deal with Transient Faults in Multiprocessor Architectures
Dynamic error processing approaches are an important mechanism to increase the reliability in a multiprocessor system, while making efficient use of the available resources. To th...
Andrea Bondavalli, Silvano Chiaradonna, Felicita D...
129
Voted
P2P
2008
IEEE
138views Communications» more  P2P 2008»
15 years 10 months ago
A P2P-Based Architecture for Secure Software Delivery Using Volunteer Assistance
We present a content delivery infrastructure distributing and maintaining software packages in a large organization. Our work based on a trace-based analysis of an existing softwa...
Purvi Shah, Jehan-François Pâris, Jef...
EUROPAR
2010
Springer
15 years 4 months ago
Thread Owned Block Cache: Managing Latency in Many-Core Architecture
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
Fenglong Song, Zhiyong Liu, Dongrui Fan, Hao Zhang...