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» An Architecture for Exploring Large Design Spaces
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VLSID
2004
IEEE
119views VLSI» more  VLSID 2004»
14 years 8 months ago
Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
Jens Bieger, Sorin A. Huss, Michael Jung, Stephan ...
DAC
2007
ACM
14 years 8 months ago
SODA: Sensitivity Based Optimization of Disk Architecture
Storage plays a pivotal role in the performance of many applications. Optimizing disk architectures is a design-time as well as a run-time issue and requires balancing between per...
Yan Zhang, Sudhanva Gurumurthi, Mircea R. Stan
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
14 years 8 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
TEI
2010
ACM
129views Hardware» more  TEI 2010»
13 years 8 months ago
Silent mutations: physical-digital interactions in spaces
Many installations research efforts today explore how to engage participants with embedded digital content and applications in interactive environments. Yet the interactive design...
Claudia Rébola Winegarden, Nicholas Komor, ...
TWC
2008
106views more  TWC 2008»
13 years 7 months ago
Spatial Multiplexing Architectures with Jointly Designed Rate-Tailoring and Ordered BLAST Decoding - Part I: Diversity-Multiplex
Abstract-- The V-BLAST (vertical Bell Labs layered Space-Time) architecture involves independent coding/decoding per antenna (layer) with equal rate and power per antenna and a fix...
Yi Jiang, Mahesh K. Varanasi